Direct Memory Access (DMA)

Data transfer between I/O devices and memory is slow due to the speed mismatch in their speeds. This is avoided by removing the CPU from the path and letting the peripheral device manage the memory buses directly. This   “data transfer between I/O device and memory without the involvement of CPU is called Direct Memory Access or DMA”.  

In this type of data transfer CPU remains free for another processes and has no control of the memory buses.  In DMA CPU make use of two control signals i.e. Bus Request (BR) and Bus Grant (BG). BR signal is used by the DMA controller to request the CPU for the control of buses. When this signal is active, CPU terminate the current execution of instruction and places  data bus, address bus, and read and write lines into high impedance state. This high impedance state works like open circuit and output is disconnected.BG Signal is used by the CPU to inform that all buses are now in high impedance state and the DMA controller can take the control of buses.

When this transfer is over the DMA disables the Bus Request Signal and CPU Disables the Bus Grant Signal and takes back the control of buses and returns back to its normal Operation.

Two Types of DMA Transfer:-When the buses are under the control of DMA data transfer can be in following ways

           1)      Burst Transfer Mode: - in Burst mode of DMA transfer memory buses are managed by the DMA controller until whole data is transferred. It is a fast transfer technique and can not be stopped or slowed down.

          2)      Cycle Stealing Mode: - In this type of Transfer mode DMA controller transfer some data and returns the control of buses to CPU and when the CPU is idle it takes back the control and starts transferring remaining data. It is a slow data transfer Technique because DMA controller has to wait for the idle CPU.